The problem of this year's design contest is similar to last year's, but using a different data set for the application tasks and communications to be mapped onto the network-on-chip. This time, instead of manually creating the data set I invested some time in generating it automatically. It is an interesting task by itself, as you must be able to tune the level of difficulty yet at the same time you must be sure that there is at least one valid mapping that satisfies all the application performance constraints (which in this case is to avoid overutilising the NoC links and processing cores).
The final results were very close, with three groups presenting valid mappings for 12-core NoCs. The winning group chose a 6x2 topology that allowed them to find a mapping that met all constraints while running the NoC at a lower clock frequency (which indicates a superior mapping). The other two groups chose mappings for 3x4 topologies, which required them to run the NoC and the cores with clock frequencies a bit higher than the nominal frequency, therefore narrowly worse than the winning group. The fourth group also presented a competitive mapping, but a bug in their mapping algorithm allowed three of the NoC links to become overutilised, thus invalidating their solution.
As usual, here is a picture of (part of) the winning team.
The post on the design contest is always closed with links to the now famous EMBS Design Contest Hall of Fame, with pictures of the top teams from all previous contests: 2021, 2020, 2019, 2018, 2017, 2016, 2015, 2014, 2012, 2011, 2010 (in 2013, no group managed to finish the challenge on time).
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