Early in November, I was invited to give one of the keynote talks at the International Symposium on System-on-Chip, which is held anually in Tampere, Finland. My talk was about a fast and accurate simulation model that I have developed for a specific Network-on-Chip architecture. By choosing that architecture, I could exploit its time predictability and create a very abstract model of the on-chip interconnect without too much accuracy loss. The results I have presented show an increase of more than 1000x on simulation speed, with less than 10% accuracy loss. Existing work has achieved only a fraction of the speed-up that we could demonstrate. A paper with the first details about this simulation model was published in the DATE 2011 proceedings and is available in IEEE Xplore.
Besides the invited talk, I have also given a tutorial on using UML and its extensions to model and validate multiprocessor embedded systems. In that tutorial, I've covered some of the topics I cover on the System Specification part of York's EDI module, and also some of the results of the research I am doing within the EU-funded MADES project.
I'd like to thank Jari Nurmi and Sanna Määttä for the invitation and for hosting me in Tampere again. Sanna, who worked for a year in my research group when I was in Germany and has recently finished her PhD under Jari's supervision, appears in the photo below introducing my talk.
