Tuesday, 1 August 2023

Some things should be simple, even an end has a start

This is the last post this blog will ever have. I'm writing it during my last days of employment at the University of York, and I decided it would be appropriate to simultaneously close the lifecycle of the blog.


I started this blog in May 2011, a few years into my academic career in York (I moved from TU Darmstadt in October 2008). Its goal was to host my reflections on the teaching and research contributions I was making in the area of embedded systems. While academics have well-established outlets for research outcomes (conference proceedings, journals), blogs became an informal outlet for the "meta" level, i.e. reflection and discussions on the practices of research and teaching. If you look into the past posts, you will find discussions about teaching styles, rants about peer review, celebrations of research successes and even job adverts. But perhaps the most common theme in the blog is the celebration of the success of my students. This includes not only my research students, but also the undergraduate students who won my Embedded Systems Design Challenge every year (and who would flaunt their picture in this blog as a badge of honour!)


After nearly fifteen years at the University of York, I have now accepted a chair at the University of Leeds. While I am very excited about the new opportunities and challenges that will come with the new position, I also look back on all of the accomplishments during my tenure at York. I have graduated nine PhD students (and have four still in the pipeline), co-created the SEtS doctoral centre, brought to York more than £1 million in research funding as a principal investigator and nearly £3 million as co-investigator (within projects with a total funding surpassing £14 million), published more than 100 articles in the top conferences and journals in my area, taught 10 different modules to York students, led the Real-Time and Distributed Systems research group, organised two conferences, won 11 awards for my research and teaching, hosted eight academic visitors, co-created the Wireless Society, examined 28 PhD theses, presented seven keynotes and 25 invited talks, managed three MSc programmes, organised two summer schools for international students, supervised eight post-doctoral research associates, 33 MEng/MSc projects and 22 BEng projects. And I've written 30 posts to this blog. This feels like a good time to close this chapter, so this 31st post will be the last one. 



But I can't close this chapter without thanking the people that made my whole experience at York very enjoyable. I will use the "you know who you are" blanket statement, but I will also name a few people who made an outstanding impression on me over the years, and will use two and only two words to describe what I admired the most about each of them (not an easy task!).


I must start with the unassuming brilliance of Alan Burns and the friendly wisdom of Andy Wellings, as they were both mentors and examples to me. Then, in no particular order: Debra Lashua's vibrant competence, Ana Cavalcanti's drive and reliability, Lilian Blot's insightful determination, Jim Woodcock's elegant generosity, Luiza Morrell's goal-oriented mindset; Chris Power, caring and outspoken; Jo Phillips, calm and helpful; Helen Ducker, quietly unfazed; Mike Freeman's resilient inventiveness; Ibrahim Habli's diplomatic tenacity, Susan Stepney's collaborative creativity, Jeremy Jacob's honest kindness, Michael Hicks' can-do attitude, Catherine Smith's work ethic, Sia Shahandashti's principled stance, and Richard Paige's informal leadership.


And I will also use the "last but not least" cliche to thank all my 
undergraduate, master and doctoral students. Thanks for all the discussions, for challenging me, and for expecting the best of me. I owe you a lot. And even if you won't admit it, I'm claiming a tiny bit of credit for all your successes.



I will continue to live within York's city walls and will retain an honorary visiting professorship in the department, so I will still be around and hope to keep in touch with everyone. But for now, I must say: LSI, over and out.  


Monday, 16 January 2023

EMBS Design Contest 2022

Again in 2022, EMBS students took part in a design contest. The whole class was divided in four groups, and were given a network-on-chip (NoC) task mapping problem to solve within a week. As the effects of covid become less significant, we are seeing more and more students engaging with in-person lab sessions, so the participation levels in the design contest were higher than the past two years. 

The problem of this year's design contest is similar to last year's, but using a different data set for the application tasks and communications to be mapped onto the network-on-chip. This time, instead of manually creating the data set I invested some time in generating it automatically. It is an interesting task by itself, as you must be able to tune the level of difficulty yet at the same time you must be sure that there is at least one valid mapping that satisfies all the application performance constraints (which in this case is to avoid overutilising the NoC links and processing cores). 

The final results were very close, with three groups presenting valid mappings for 12-core NoCs. The winning group chose a 6x2 topology that allowed them to find a mapping that met all constraints while running the NoC at a lower clock frequency (which indicates a superior mapping). The other two groups chose mappings for 3x4 topologies, which required them to run the NoC and the cores with clock frequencies a bit higher than the nominal frequency, therefore narrowly worse than the winning group. The fourth group also presented a competitive mapping, but a bug in their mapping algorithm allowed three of the NoC links to become overutilised, thus invalidating their solution. As usual, here is a picture of (part of) the winning team.





The post on the design contest is always closed with links to the now famous EMBS Design Contest Hall of Fame, with pictures of the top teams from all previous contests: 2021, 2020, 2019, 2018, 2017, 2016, 2015, 2014, 2012, 2011, 2010 (in 2013, no group managed to finish the challenge on time).

Thursday, 14 July 2022

University internationalisation

Before I joined the University of York in 2008, I worked for the Technische Universitaet Darmstadt in Germany. Just like in my current position, that job involved research, teaching and academic administration. My main academic administration task was to support the creation of an international master programme, which I then coordinated for seven years (from 2001 to 2008). It was one of the first international master programmes in Germany, and the first at TU Darmstadt. It was taught mostly in English, aiming to make it easier for international students to obtain a degree in Germany. It was a lot of work, since I had to oversee all aspects related to the programme: admission process, student support, curriculum management, accreditation, marketing, website, among other tasks. I have learned a lot in the process, and had the chance to attend several events to share my experiences with other academics playing similar roles in other German universities. It also made it easier for me to play similar roles here in York (where I have already coordinated three master programmes, and I am currently coordinating one of our PhD programmes).

Last year, I was invited to be a guest speaker in the celebration of the 20th anniversary of that study programme. Due to covid travel restrictions, the event was postponed to July 2022, and it was a success (even though the programme was almost 21 years old by then!) Among the guest speakers, Prof. Manfred Glesner (the main force behind the creation of the programme, and one of my PhD supervisors) and three former graduates. Manfred spoke about the history of the programme, and how it contributed to change the university landscape in Germany, which now attracts a much larger number of international students. The former graduates talked about the different ways that the programme kickstarted their professional lives, giving them a multidisciplinary foundation in the areas of microelectronics, communications and computer engineering. It was very rewarding to see the impact of the work we did all those years ago, and to see that even though I left TU Darmstadt in 2008 some of my contributions to that institution are still bearing fruit.

For my talk, I decided to focus on the goals and challenges of university internationalisation, and I highlighted that all success stories I am aware of required a careful inter-play between grassroots and institutional drives: motivated individuals willing to invest time into building international initiatives (degree programmes, summer schools, university networks, etc.), and flexible university structures willing to support those individuals' visions and ambitions. I also remarked that university internationalisation is a microcosm of world politics, so it is directly influenced by events around the world but it can also influence the way we understand and react to those events, and therefore discussing and putting internationalisation in practice is perhaps the best way for academics to express their world views.

Below, a few pictures from the event (photo credit: etit TU Darmstadt).

Wednesday, 1 December 2021

EMBS Design Contest 2021

Another year has passed, and with the relaxation of the restrictions related to the covid 19 pandemic we were allowed back to campus for all embedded systems lectures and practicals in the Autumn term in 2021. This was not possible for everyone, so all the teaching material was also made available via virtual learning environment (including pre-recorded videos of all lectures created in 2020, as well as the recording of the live lectures from 2021).

Our annual design contest took place on campus between November 23 and 25, and the design challenge was again based on the mapping of embedded software tasks onto a multiprocessor system based on Networks-on-Chip (NoC). This challenge was introduced last year, and was successfully solved by most groups despite of the difficulties of working online. One of the groups even managed to find a solution that was superior to the model solution I had found for the challenge! More details in last year's blog post.

For this year's challenge, I decided to make the problem a bit harder. Firstly, because the element of surprise would no longer be there (over the years I have witness how much students learn from their seniors). And secondly, because last year's groups did so much better than I expected, so I wanted to make sure this year's students felt sufficiently challenged.

The increased difficulty came from two small changes to challenge. The first was simple and obvious: I increased slightly the number of tasks (from 44 to 54) and inter-task communications (from 68 to 70). The complexity of a mapping problem always increases with the number of "things" to be mapped, so this was an easy way to make the problem more challenging. But it is likely that the solutions used by last year's groups would cope with this year's problem as well. So I also changed the design alternatives that the students were allowed to consider. Last year, they were allowed to lower the clock frequency of the processing cores and the NoC interconnect, as long as the application tasks would not overutilise any core or interconnect link, aiming to reduce energy dissipation. But they would not be able to overclock the cores or the interconnect: in case a particular processor configuration was not fast enough to run all application tasks without overutilising the platform, their alternative was to go for a larger platform (i.e. with more cores and a larger interconnect). This year, students were allowed to overclock processing cores and/or the interconnect by up to 20%, which provided them more design alternatives to explore (e.g. overclock a smaller platform vs. underclock a larger platform). To take into account both dimensions of the design space, the quality of the solutions found by each group was ranked by the number of processing cores they needed (lower is better), and by the frequency scaling factor for cores and interconnect (lower is better).

The class was randomly divided in four groups, but due to absences each group had between 1 and 3 active members (the design contest is not a mandatory part of the embedded systems module, and does not contribute to the final mark). They were given two days to work on the design challenge, and all groups submitted a solution by the deadline. Just like in 2020, three of the solutions submitted were valid task mappings that did not overutilise the multiprocessor platform when scaling the clock frequency by the submitted factors (one of the groups submitted only a partial mapping that did not include all tasks, so it could not be evaluated). The valid solutions submitted by groups 2, 3 and 4 required platforms with 20, 36 and 18 cores, respectively. With a smaller number of cores, group 4 was named the winner even when taking into account the frequency scaling factors used by each group. Below, a photo with the members of group 4 David Kacs and Ben Marsh (and their prize).

Again this year, I decided to award a honourable mention. This time it goes to group 2, which was actually a one-member-group, but still managed to submit a valid solution that was only marginally worse than the winning solution (20 cores running at nominal frequency, while the winners used 18 overclocked cores). Below, a photo of Aaron Christiansen, with no prize but with the recognition of being the first ever person to single-handedly complete the EMBS design contest.
Perhaps because of the additional complexity I added to the challenge, this year no group managed to find a solution that was as good as the solution I created prior to the contest (using the technique I described in last year's post). My solution requires only 16 cores, but needs a small overclocking of cores as well as the NoC interconnect. I did not share that solution with them, and instead left it as an open-ended challenge. I'm sure someone will be pleased to send me an email over the winter break showing that they could beat me...

The post on the design contest is always closed with links to the now famous EMBS Design Contest Hall of Fame, with pictures of the top teams from all previous contests: 2020, 2019, 2018, 2017, 2016, 2015, 2014, 2012, 2011, 2010 (in 2013, no group managed to finish the challenge on time).

Tuesday, 30 November 2021

Safe, Ethical and Secure (Embedded) Computing

A couple years ago, I was tasked by my department to put together an innovative programme to train PhD students. After doing a consultation with all colleagues in our research away day in 2019, I could see a scenario that went completely against the picture of a stereotypical PhD student as a lonely character working on a hermetic topic which they carefully hide from the world until they can publish it causing fanfare and/or Earth-shattering consequences. Instead, what emerged was the desire for a strong sense of community, and emphasis on resilience and mutual support. Among the research topics we should emphasise, the list that emerged included green computing, explainable and safe AI, trustworthy decision-making in humans and machines, and ethical digital technologies. This was a very valuable exercise, and helped us in understanding the long term aspirations of the department in terms of research.

But then the covid 19 pandemic happened, and all research activities in the department were deprioritised so we had enough manpower to cope with the heavy workload caused by the move into online teaching. The plans for the innovative doctoral traning were suspended, and only resumed in early 2021. By then, with Paul Cairns as the new head of department and Ibrahim Habli as deputy head for research, the long term research vision for the department had been aptly summarised as safe, ethical and secure computing. And the new doctoral training centre was chosen to be a key instrument in realising that view, providing fully-funded studentships to students willing to work on high-impact research in those areas. So I took on the challenge and, with excellent support from the department's admissions team, managed to advertise, interview and recruit the first batch of PhD students for SEtS, the department's Doctoral Centre for Safe, Ethical and Secure Computing. They started their journey towards a PhD two months ago, and their topics cover areas as diverse as machine learning for cocoa plant disease identification, wireless networking for swarm robotics, monetisation strategies and player well-being in online gaming, and formal proofs for security-related properties in robotic systems. Interestingly, two of them are former EMBS students, and one of them appears in the EMBS Design Contest hall of fame! I am now meeting them on a weekly basis, trying out a number of new training initiatives, and gathering feedback on how to improve the training process for future cohorts.

So while the focus of the doctoral centre is much wider, there are many opportunities for research work in the area of embedded systems. The application process will be open over the next two months, so feel free to contact me if you are interested in pursuing a PhD in our doctoral centre. I'll be happy to discuss a potential research topic, or to introduce you to colleagues that do work in the areas you might be interested in. Find more details about my research areas, and my contact information, here.

Who would not want to be part of a centre with the acronym SEtS and with a Venn diagram showing the intersection of its three main areas as its logo?

Wednesday, 2 December 2020

EMBS Design Contest 2020

 

One year has passed since I wrote the last entry to this blog, and everything is so different now. We had to adapt to a very complex situation, and all our teaching had to be done online this academic year. It was particularly challenging for embedded systems, which in York has always been taught as lab-centric topic. With no access to the labs, we had to work hard to achieve the same learning outcomes using design tools and simulators that could be run by students in their own computers. We had a couple issues, particularly with creating and deploying virtual machines with pre-installed tools, but given the circumstances everything went well.

Another challenge was this year’s EMBS Design Contest. The traditional format where students run against the clock to create an ad-hoc wireless network across the Computer Science building was clearly not possible this year. After thinking about it for several weeks, I was ready to cancel the contest when I had an idea that would be suitable for our circumstances. Since I had added some new material to the part of EMBS that covers platform-based design and task mapping algorithms/heuristics (as I was forced to reduce the content on embedded wireless networking due to no access to the labs), I thought I could explore that type of problem and formulate a challenge that people could address in a distributed way.

The problem I devised was to map a large application model (44 tasks, 68 inter-task communication flows) to a multi-core platform based on a 2D-mesh network-on-chip. The application tasks and communications were characterised, respectively, by their processor utilisation and network link utilisation at nominal frequencies for the cores and interconnect. The objective was to find a mapping, over the smallest 2D-mesh platform and running at the smallest fraction of the nominal frequencies, but without over-utilising any processing core or network-on-chip link. This is an NP-hard problem that I’ve addressed in my research (together with several of my post-doc researchers, Master and PhD students), but using response time analysis instead of utilisation-based tests. In either case, there are no known optimal algorithms for this problem, only heuristics that do not guarantee optimality.




Before releasing the problem, I had to make sure it was challenging enough, and that it had at least one valid solution. To do that, I have created a valid mapping for a fairly thin application model onto a 4x3 network-on-chip platform. I then inflated the utilisations of tasks and communications of that thin model until that mapping was nearly breaking the utilisation bound of the platform at arbitrary but realistic frequency levels. The inflated application model was then be the problem I posed to the students (divided in four groups), and I had a good solution that I knew was valid (my chosen mapping for a 4x3 platform) and certainly achievable by the students with a bit of effort.

Once the challenge was released, I monitored the progress of all four groups (and had one videoconference session with each group) over the 2.5 days of the contest. Students were not allowed to choose their groups, and each group had 8-10 members. I’ve noticed that only 2-5 members of each group were actively working towards a solution to the design challenge. In past years, when the design contest happened in the lab, it was common to see 2-3 students taking the lead, but then all other students would engage or at least learn from the solutions attempted by the group. In the case of remote/online groups in 2020, that “side-learning” situation (i.e. students learning from students) did not really work. This could be an undesired consequence of online groupwork, but could also be related to the covid circumstances, or to the heavy workload at the end of the teaching term (especially when running the contest over 2.5 days instead of an intensive lab-based 2h competition).

Nonetheless, the achievements of the groups were laudable. Three of the four groups provided valid solutions to the problem. Group 4 actually found my original solution on a 4x3 platform, using a clever constructive heuristic that clustered together tasks that had high-utilisation communication flows between then, followed by some manual adjustments to tidy up the mapping. But the winner of the EMBS 2020 design contest was Group 3, who came up with a valid mapping for a 5x2 platform, therefore using fewer processors than the solution found by Group 4 (and myself). Their approach was based on the use of Genetic Algorithms for task mapping, which was covered in the new lectures and practical exercises I added to EMBS this year. Remarkable work, based on an unusual network-on-chip topology, but fulfilling completely the rubric of the design contest.

As always, we close the blog post with a picture of the winning group, Group 3. Fittingly for 2020, the picture is a snapshot of a videoconference. The group members will receive their prize (a snack giftbox each) via post this year.




 

And for finding my original solution to the challenge, I decided to award an honourable mention to Group 4 and add their photo as well.


 

Finally, links to the complete EMBS Design Contest Hall of Fame, with pictures of the top teams from 20192018201720162015201420122011 and 2010 (in 2013, no group managed to finish the challenge on time).

Tuesday, 26 November 2019

EMBS Design Contest 2019

Every year, students in the Embedded Systems module take part in a design contest. In 2019, three teams competed in the task of setting up a multi-hop wireless network that is able to transmit information across the Computer Science building. This time, two teams managed to complete the task within the 2-hour slot allocated for the contest. The winner team, who finished only a few minutes earlier, received a box of chocolates and was granted the honour of having a picture published in this blog:


The second group to finish also received an honourable mention, and a smaller picture in the blog:



Here is the complete hall of fame, with links to the pictures of the top teams from 2018201720162015201420122011 and 2010 (in 2013, no group managed to finish the task).

EU-funded SAFIRE Project Concluded

We have now finished the work in the EU-funded SAFIRE project. The goal of the project was to investigate and develop technologies and infrastructure that enable Reconfiguration-as-a-Service for dynamic smart factory systems and manufactured smart products. York's role in the project was to design an optimisation engine based on Evolutionary Algorithms that can tackle large reconfiguration spaces by using a scalable cloud-based deployment.

York's optimisation engine was integrated to the situation determination and predictive analytics modules created by project partners ATB and IKERLAN, respectively, using a secure infrastructure provided by The Open Group. That way, every time a new situation in the factory is detected (for instance, if a mixer breaks or if the cost of wires has increased significantly), the optimisation engine is informed about it and it can evolve a new configuration that takes the new situation into account.

That approach was applied to three different case studies proposed by the industrial partners of the project: ONA (metal cutting machines), OAS (paint-making factory) and Electrolux (smart industrial kitchen). The results were disseminated by many publications, talks and keynotes, as well as newsletters and press releases.


I mention the SAFIRE project in this blog to show that embedded computing is dealing with much larger systems these days - embedded into a factory! - in a trend which is often referred as Cyber-Physical Systems.

More information and details in the SAFIRE website, which also includes links to all public reports and deliverables, as well as open source distributions of the code developed within the project.

SAFIRE was funded by the European Commission within its Horizon 2020 framework programme under reference 723634.



Friday, 16 November 2018

EMBS Design Contest 2018

Once more, it is time to report on the annual EMBS Design Contest. This year, four teams worked against the clock to implement, test and deploy a simple multihop wireless communication protocol delivering packets across the Computer Science building, from the hardward labs all the way to my office.

And just like last year, we had a winning team completing the task in less than two hours and a honourable mention finishing only a few minutes later. So, following our tradition, the winning team got a box of chocolates and their picture here in the blog:



And as we did last year, we allow a smaller photo of the honourable mention team:



And to close the report, links to the pictures of the top teams from 201720162015201420122011 and 2010 (in 2013, no group managed to finish the task).

Monday, 9 April 2018

Best Paper Award at DATE 2018

Last year, I wrote in this blog about my major disappointments with the academic peer review system, motivated by a series of reviews that I judged unfair and biased and that prevented an interesting piece of research (jointly authored by myself, Alan Burns and Borislav Nikolic) from being published. Now I am happy to report that the work has been accepted and presented at the top European conference in design automation of electronic and embedded systems (DATE 2018), and it has received the best paper award in the conference's Embedded and Cyber-Physical Systems track. DATE 2018 received 766 paper submissions and had over 1000 registered attendees, which further boosts the importance of the paper acceptance and the award.




This doesn't make it easier to accept the peer review flaws we had to go through, but at least it enables the publication of the work and a better definition of the current state-of-the-art in the area of priority-preemptive wormhole networks.

pre-print of the paper can be found in the White Rose repository.


Thursday, 16 November 2017

EMBS Design Contest 2017

And it is time to announce the winners of the EMBS Design Contest 2017. The Contest took place a bit later this year because of some changes in the teaching plan, aiming to better cope with the reduction in the number of assessments (from three to only two now, one in Dec/Jan and another in Apr/May). The rules were still the same: class divided in teams, each of them trying to design, implement and deploy an ad-hoc wireless network that is able to send packets from the lab all the way to my office in the opposite end of the Computer Science building. All within two hours!


This time, the winning team managed to get their solution working within a few minutes of the deadline, and were rewarded with a box of chocolates and their photo in this blog:

EMBS Design Contest 2017 Winners

And for the first time ever, the race towards a working solution was really close, and a second group managed to have their solution working and delivering packets at the destination only a couple of minutes after the winning group had delivered their first packet, so I think it is fair enough to reward them with a Honourable Mention and a (smaller) photo in the blog as well (but no chocolates):

EMBS Design Contest 2017 Honourable Mention
EMBS Design Contest 2017 Honourable Mention


Here, some links to the pictures of the top teams from 2016, 2015, 2014, 2012, 2011 and 2010 (in 2013, no group managed to finish the task).


Tuesday, 1 August 2017

My major disappointments with peer-review (so far)

I always tell my PhD students that the academic peer-review system is bad, but it is the best we've got. Every time one of them feels they were unfairly treated by an editor's decision, or when they perceive that reviewers didn't really put the effort to understand their paper, I have to tell them not to take it personally, and to accept the flaws of the system because we haven't yet been able to figure out a better way to improve the quality of our collective scientific output. And I always tell them a story from my personal experience, to show them that they are not the only ones facing disappointment, and that they will live to tell others that things are not so bad.




The story I've been using over the past few years was the rejection of a paper Borislav Nikolic, myself and Stefan Petters submitted to the NOCS 2014 conference (which we have subsequently uploaded to arxiv, as it turned out its contribution was significant, but more on that later). The paper had received fairly good reviews, but one of the reviewers stated that our paper tried to fix exactly the same problem as another paper we did not know of, published a few months earlier at RTAS 2013, so the reviewer gave us the lowest possible score. Verbatim from the review: "...the authors have replicated the results of Kashif et al. in their RTAS 2013 paper". That's fair enough: a tough reviewer can take a stance that our paper was worthless without a clear comparison with the state-of-the-art, which in this case clearly should have included Kashif et al.'s paper. The punchline of this story, however, is the fact that the reviewer was not really criticising our lack of diligence on reviewing the state-of-the-art, but implying that we were trying to copy the approach of that paper. Again, verbatim: "As can be seen, the goals are identical. Now coming to the contributions, the current paper and the RTAS paper fix exactly the same pessimism in the model of Burns" (referring to a previous paper by Zheng Shi and Alan Burns published at NOCS in 2008). And here is my favourite part of that review:


"Also, please look at Fig.1 in the current paper and Fig. 3.1 on page 20 of the thesis (ref. [8] of the RTAS paper) to be found here: https://uwspace.uwaterloo.ca/bitstream/handle/10012/6906/Gholamian_Sina.pdf?sequence=1

I know that this is basic stuff, but the figures are too similar for this to be merely a coincidence."


That's it: the reviewer accused us of plagiarism! Of using in our paper, without credit or reference, a figure published in the thesis of one of the authors of that RTAS paper. Immediately after reading that review, I went to check which figure the reviewer was referring to, first in our paper and then following the link to the PDF of that thesis. I could clearly see that the figures are the same, except for some cosmetic change (different font, line thickness, colour). But that was a figure I had created several years earlier for a paper I wrote with Alan Burns and Zheng Shi in 2009 (and published in 2010 in the IJERTCS journal). I had used the same figure in other documents afterwards, and also in our NOCS 2014 submission. So what really happened is that the thesis author had plagiarised me. And I was accused of, effectively, plagiarising myself.

We did contact the programme chairs of the NOCS conference, Joerg Henkel and Sudha Yalamanchili, to explain the situation, and they in turn contacted the anonymous reviewer. The reviewer replied that the plagiarism claim was not the reason for the low score, and that he/she "would have given the paper a score of 1 even if figure 1 did not exist". The programme chairs decided they could do nothing else. And we never received an apology from the reviewer or the programme chairs for being falsely accused of plagiarism. They all pretended that falsely accusing someone was normal, and unimportant.




Unfortunately, I now have a better (or worse) story to tell my students about the flaws of peer-review. This new story started in May 2016, when I was made aware of the work of Xiong et al. on the real-time analysis of priority-preemptive wormhole Networks-on-Chip, which has been presented in the GLSVLSI conference. Their paper presented a scenario showing that Shi and Burns analysis from NOCS 2008 was optimistic. At this stage, I'd like to clarify to those who are not familiar with worst-case analysis that a pessimistic analysis can be useful, i.e. if a system is designed to cope with a pessimistic worst case, it can also cope with the actual worst case, which will be less severe. It can be improved upon, of course, to avoid unnecessary over-dimensioning of a system, and that was the goal of both Kashif et al.'s RTAS 2013 paper and our rejected NOCS 2014 submission mentioned above. What Xiong et al. have shown, however, is that the analysis by Shi and Burns was optimistic, meaning that there are possible cases that are worse than the worst case predicted by their analysis, making it unsafe. That was a significant game changer, because it showed a flaw on an important piece of research (by that time, the original Shi and Burns paper already had more than 100 citations). More than that: each and every approach that tried to reduce the pessimism from that work, i.e. had a stricter view of what the worst case was, was also flawed. I must say at this point that the optimism in the analysis was not uncovered by the identification of flaws in the proofs and theorems given in any of the previously published papers, but by finding a counter-example through simulation: Xiong et al. found some results in their simulations that were worse than what was predicted by all state-of-the-art analyses, and then tried to identified the likely cause. Their paper then explained that cause, showed the optimism of the previous analyses in small examples, and proposed a new analysis to fix that problem.

My goal here is not to explain the exact nature of the problem they uncovered, or the details of their fix. But you can imagine how surprised I was when I found out about their paper. Many researchers, including myself, worked for many years on that precise topic, and nobody has seen that problem before. The first paper addressing the problem was published in the early 90s! Theorems and proofs were written, but the complex nature of such systems prevent such proofs from being perfect. Those are in reality proof sketches, and try to convince the reader with some intuition and logic that they are correct. To prove them wrong, however, it is a straightforward job: simply show a scenario where the real behaviour of the system is worse than the worst case predicted by the analysis. Such scenarios may be extremely hard to find, though. But in this case, one of such scenarios was well described in the GLSVLSI paper, and I was keen to understand it in depth. It took me a few days to get used to the notation used in that paper do describe the system, to familiarise myself with the scenarios under which the previous analysis would break, and to understand the analysis they proposed. Once I understood how they made it safe even under the corner cases that broke the previous analyses, I was convinced I could do a better job. Over the following days, I worked on improving analysis on my own, exploiting buffering and backpressure effects differently than all previous analyses. Springtime was particularly pleasant in York that year, so I did most of the work outdoors (on campus, or on the Millennium Bridge). Once I had convinced myself that my improved analysis was correct, I wrote a draft paper about it and shared it with Alan Burns and Borislav Nikolic, who were the two people I've previously worked with on NoC analysis. Unlike most researchers in this area, I prefer to write my papers without any proof sketches, relying only on intuitions and experimental work to get my point across. As I mentioned before, proof sketches are not fail-proof, and I find that they often make it harder to spot issues because of awkward notation. With input from Alan and Borislav, I was convinced that the new analysis attacked the most significant source of pessimism in Xiong et al.'s analysis, and it also opened the path to tackle other sources of pessimism (one of them using the techniques Borislav and I have explored in the paper with the self-plagiarism, but that was left as future work). And finally, after discussing in detail with Borislav about the weaknesses of Xiong et al's analysis, he came up with a counter-example that showed that their analysis was also optimistic! I then updated the paper draft with the details of that counter-example, with additional examples and large-scale experiments to compare the pessimism of the new analysis against Xiong et al. I then uploaded that paper to arxiv on June 9th.

Up to this point, I've had one of the best experiences in my life as a researcher: within a few weeks I was made aware of a new research problem that was hiding in plain sight, I had understood the state-of-the-art solution to that problem, and through compelling collaborations with great colleagues I was able to find a solution that was better than the state-of-the-art.

Once I published the paper in arxiv, we contacted all authors of the GLSVLSI paper to notify them of our findings that their analysis was flawed and unnecessarily pessimistic. We also invited them to be co-authors of a journal submission based on our arxiv paper, as we felt that we would not have done that work without the trigger caused by their GLSIVLSI paper. Our choice of a journal was the IEEE Transactions on Computers (ToC), which had previously published a paper by Kashif et al. (actually an extended version of their RTAS 2013 paper mentioned above), and which was the state-of-the-art on priority-preemptive wormhole analysis at the time. This resulted in an exchange of emails with two of the authors of the GLSVLSI paper, Qin Xiong and Zhonghai Lu, who informed us that they would be really glad to have a joint paper with us in that topic. They also mentioned that they had already submitted an article to IEEE ToC with an in-depth description of their analysis, and showing that their counter-example invalidated the analyses published by Shi and Burns in NOCS 2008 as well as the latest work by Kashif et al. on that same journal. They recognised the flaw we have pointed out in their GLSVLSI paper, and told us that it also appeared in their ToC submission, which was under review at that point. They therefore proposed to work on the joint paper with our improved analysis, and then decide what to do once they had a response on their submission.

So I carried on improving our draft, with further inputs from Alan, Borislav, Qin and Zhonghai. When our draft was nearly ready for submission, Qin informed us that their ToC submission was returned to them for major reviews. On behalf of his co-authors, he then proposed to include our fix to their analysis in the next revision of that paper, and to add Alan, Borislav and myself as co-authors in that paper. We felt that it would be confusing to have two papers under review at the same time, in the same journal, with the same authors, and one of them fixing and improving the other. Furthermore, we would prefer to have the fix of their flawed analysis as a contribution of our new submission, and would not feel comfortable to publish a paper with a flawed analysis. So we replied that we would prefer to carry on with the submission of our paper including the fix and the improvement on the analysis (i.e. based on the arxiv paper), that we would decline their offer to be co-authors in their current submission, and that it would then be best to separate the authors of both contributions. They insisted in having two joint papers, perhaps in two different journals, but we were keen on having our paper published in the same venue that had published the latest state-of-the-art in this area. As we couldn't find a solution that was completely acceptable to both sides, and as we could not really ask them to withdraw the paper with the flawed analysis, we decided to detach ourselves completely from that submission and to carry on with our new submission, including all of us as co-authors as initially proposed. That paper was submitted to ToC on October 10th. About the same time, Qin informed us that he would carry on with the major revisions in their submission, and that he wanted to include our fix as part of the revision, and offer once more a co-authorship. We once more declined, and simply asked for a citation to our arxiv paper as the source for the corrected analysis. Despite such a complex situation, the discussions and exchanges were done in a very respectful manner, and all parties tried to be as fair as possible with each other and to give academic credit to whoever it was due. In an ideal world, both papers would be published by the journal, and the whole community would be aware of the successive extensions to the state-of-the-art.

However, the world is not ideal, and this is when the disappointments started. On January 9th 2017, we received an email with a decision about our ToC submission, based on three reviews. The first reviewer was positive about the contributions of our work, pointed out a few minor corrections needed, and stated that a theorem that definitively proves that the proposed analysis is safe for all possible scenarios would be desirable and should be proposed as an open problem for future work. The second reviewer went deeper into the technical details and provided a number of requests for more details, clarifications and overall improvement (most of them very pertinent and useful). The third reviewer was a complete disappointment, providing a two-sentence review (and the second of them mostly irrelevant to our submission): "Authors proposed an analytical method to analyze the latency of a priority-preemptive wormhole network. However, they just provided the experimental result for 4x4 and 8x8 network with XY router under an uniform random traffic, which is not sufficient to support the fidelity of their model." But the most disappointing part of that email was actually the decision by the editor-in-chief Paolo Montuschi that the paper should undergo a reduction to a Transactions Brief as part of the requested major revisions. A Brief can have only 8 double-column pages, as opposed to a regular contribution which can have up to 16. That decision seemed completely arbitrary, given that our work claimed to supersede an article (by Kashif et al.) that was published as a regular contribution, and to supersede and fix another article (by Xiong et al.) that was being considered as a regular contribution. Furthermore, the reviewers of our submission have requested clarifications and more details about the approach, which would increase rather than reduce the number of pages of our contribution. Therefore we spent several weeks preparing a revision that addressed the comments of all three reviewers, which led us to make improvements on the analysis, the overall paper organisation, and to redo all experiments over a wider range of scenarios. To satisfy the third reviewer, we also performed a whole new series of experiments under different network topologies and using different routing algorithms, despite the fact that we did not believe those cases would change the experimental conclusions of our original submission (and, as expected, they didn't).

In the meantime, we were notified by Qin and Zhonghai that their submission has been accepted as a regular contribution to ToC. We then had to remove from our paper all the parts that showed the flaw in their original GLSVLSI paper, and our proposed fix to that analysis, as that would no longer contribute to the state-of-the-art once that was published in their paper. With the additional material requested by the reviewers, and with the removal of the material related to the fix to the flawed GLSVLSI analysis, the overall page count of the revised paper was slightly reduced to 10.5 pages. We then submitted that revision on May 8th, with an extensive letter to reviewers explaining how we addressed all their comments, and respectfully asking the editor-in-chief to consider our submission despite being above the 8-page limit of a Transactions Brief. One day later, we received a decision by Paolo Montuschi rejecting the paper without sending it to the reviewers. He argued "that the request to reduce the paper to a Transaction Brief (...) is not just an issue related to paper's length but also of impact of the proposed research, according to current TC quality standards". The fact that our paper fixed and superseded two papers published in that same journal as regular contributions, and that it effectively re-established the state-of-the-art in that area, was apparently not impactful enough for him. After discussing with my co-authors, I decided that it was pointless to argue with the editor-in-chief and to try to make them see that it is absurd to blindly apply rules related to page limits in a world of digital publications. I had to convince myself to agree that their bureaucratic approach to managing a journal would make it harder for us to establish the state-of-the art in our area, but that I should persevere nonetheless. That was not easy at all.

In the same decision email, we were given the chance to make a new submission as a Transactions Brief, i.e. reducing the paper to a maximum of 8 pages. I then invested a few days to do that: I removed some of the literature review, reorganised the background work and problem description, redrew all figures to occupy less space, reformatted tables and captions, abbreviated references, and removed all the additional experiments we had added to respond to the third reviewer, reduced the number of examples explaining our contribution and significantly reduced the summary of conclusions, comparison to related work and potential future work. I also contacted Qin and Zhonghai, stating my disappointment with the rejection of our joint paper, acknowledging that their contribution to the work has already been published in their ToC paper, and declaring that I would try to get our work published with the original set of authors (i.e. Alan, Borislav and myself). With all those changes, and with a reduced author list, I managed to produce a reduced-scope version of the paper within the 8-page budget. I have then submitted it as a Transactions Brief on May 16th.

We received a decision notification on July 27th, and again the editor-in-chief decided to reject the paper. This time, we've got two reviews. One of them was a three-liner: "The paper provides a tighter worst-case latency analysis for pre-emptive wormhole networks. A proof or explanation to confirm the safety of their analysis would be a plus. Section II, III and IV provide a good background and problem description, however, they are too lengthy compared by the contribution part of this paper." The second reviewer went a little further and raised a number of minor points, but they were either irrelevant (e.g. our choice for the operating frequency of the network routers in the experiments), based on their lack of familiarity with real-time networks (e.g. criticising the lack of support for adaptive routing), or were addressed in our previous submission and had to be removed to comply with the page budget for Briefs (e.g. definitions of "non-zero critical instant" and "sub-route interference"). Again, there was no convincing argument to justify the rejection of a contribution that superseded two articles recently published in that journal. The criticism that our work did not include a proof of its correctness is a valid criticism, but it is not a fair reason for rejection: all previously published papers (including those published by ToC) had such a proof, but they were nonetheless proven wrong by our counter-examples. We cannot guarantee that that there isn't a counter-example that could prove our analysis wrong, but if we are not allowed to publish it, the community would not know where to look for such a counter-example (as we did when we learned about the previous ones).

As a summary, we had to submit three versions of our work: the first received two useful reviewers (one more than the other) and a two-liner; the second was rejected right away and was never read or reviewed; the third received a three-liner and an uninformed review. This is way below the level of quality and engagement I expected in a top journal: poor reviewing and, above all, poor editorial work, as it is the job of the editor to choose the reviewers and to accept their reviews. As a result, more than one year has passed since we proposed an analysis that fixed the flaws and improved significantly the pessimism of the work published by Xiong et al., but that work is still the published state-of-the-art in this area. That's an incredibly disappointing situation.

As a final statement, I'd like to reiterate how I'm glad and proud of the way that all the active researchers behaved in the situations reported here, and that my disappointment is restricted to the low quality of review and editorial work we have experienced. Working with Alan and Borislav was a delight; and dealing with Zhonghai and Qin, on behalf of their co-authors, was always a very positive experience and I'm sure that the impact we made to each other's works greatly outweighs the fact that we were denied a joint publication giving fair credit to our contributions to a very challenging research problem. During this period I have also interacted with Hiren Patel (one of the authors of the Kashif et al. papers), talking about the "plagiarism" claims we faced, asking more details about their analysis and sharing with him the new developments we achieved. This was also a very positive interaction, including some good feedback on our arxiv paper.

Wednesday, 16 November 2016

EMBS Design Contest 2016

As it happens every year, I run a design contest as part of my undergraduate module on Embedded Systems. This year, we had a larger number of students choosing the module (maybe because we were ranked top teaching in the department last year!), so for the first time we had four teams competing for the coveted prizes: a box of chocolates and a picture on this blog. Their task: to design and implement a multi-hop wireless network using the IEEE 802.15.4 protocol, so that a message can be routed from the labs to my office on the other side of our C-shaped building.

This year's winners took an unorthodox approach to the network topology. Instead of placing network nodes all the way through the C-shaped corridor as previous winners have done, they decided to take a shortcut through the inner courtyard of the building. Iain Bate was seen giving them some advice about avoiding WiFi interference, which may have tipped the balance towards going outdoors. Luckily for them, the weather was mild and they had no problem to place network nodes over their shortcut (side picture shows the view from my office window). In previous years, rain and snow have prevented other groups from succeeding on that.

Bottom line is: they managed to finish the task before everybody else, in a little over two hours, so they deserve to be immortalised with their picture in the gallery of winners, which also include the top teams from 20152014, 2012, 2011 and 2010 (in 2013, no group managed to finish the challenge).


 

Monday, 31 October 2016

New book: Dynamic Resource Allocation in Embedded, High-Performance and Cloud Computing

River Publishers has released this month our textbook on dynamic resource allocation heuristics for embedded, high-performance and cloud computing. The book is authored by myself and two of my former postdoc researchers Piotr Dziurzanski (now a lecturer at Staffordshire University) and Amit Kumar Singh (now a senior postdoc at Southampton University). It presents some of the work we did in the EU-funded DreamCloud project.

Hardcopies will be available for purchase on Amazon, and an ebook version is freely available in the publisher's website. This arrangement was made possible thanks to the EU FP7 Post-Grant Open Access Pilot Scheme. The textbook includes the following chapters:

Preface; 1. Introduction; 2. Load and Resource Models; 3. Feedback-based Admission Control Heuristics; 4. Feedback-based Allocation and Optimisation Heuristics; 5. Search-based Heuristics for Modal Applications; 6. Swarm Intelligence Algorithms for Dynamic Task Reallocation; 7. Value-Based Allocation; Bibliography


Monday, 4 January 2016

2nd DREAMCloud Workshop

Together with the DreamCloud project team, I'm organising the 2nd International Workshop on Dynamic Resource Allocation and Management in Embedded, High Performance and Cloud Computing. More details, and an embarrassing video, below:

https://www.hipeac.net/2016/prague/
https://www.hipeac.net/events/activities/7316/dreamcloud/
http://www.dreamcloud-project.org/forum/workshop2016



Wednesday, 11 November 2015

WSN Design Contest 2015

Today was the day of the WSN Design Contest 2015. Actually, the contest is still taking place as I write this, but we already have winners! For the first time ever, one of the groups finished the challenge with plenty of time to spare (they did it in about 1h40!)

Below, the winning group and their prize.



They now join the gallery of winning teams of each year: 2014, 2012, 2011 and 2010 (in 2013, no group managed to finish the challenge). 

The contest is part of my EMBS undergraduate module: all students are divided in groups, are given a few WSN motes and programming boards, and must design, test and implement a simple multihop wireless communication protocol over IEEE 802.15.4 physical layer in order to transmit a packet from the labs to my office, all within a 2 hours practical lecture slot. The winner team gets a box of chocolates, and are immortalised with their picture in this blog.

Wednesday, 27 May 2015

First batch of PhDs

The year of 2014 was the year I graduated my first doctoral students in York. Previously I had co-supervised the PhDs of Luciano Ost (at PUCRS, with Fernando Moraes as the main supervisor) and Leandro Moeller (at TU Darmstadt, with Manfred Glesner as the main supervisor). Now, with all their degrees issued and their theses approved and published at the White Rose e-Theses repository, I'm glad to present my first batch of Yorkies:

Ipek Caliskanelli: A Bio-inspired Load Balancing Technique for Wireless Sensor Networks

Andrew Burkimsher: Fair, responsive scheduling of engineering workflows on computing grids (co-supervised with Iain Bate)

M. Norazizi Sham Mohd Sayuti: Early Design Space Exploration of Hard Real-Time Embedded Networks-on-Chip

The three research topics reflect very well my portfolio, as they apply different resource allocation techniques to different computational platforms (sensor networks, high performance grids and on-chip multiprocessors, respectively) to achieve critical non-fuctional properties related to time and energy dissipation.

And it is great to know they all went on to promising academic careers. Ipek is now a post-doc researcher at the University of Liverpool, Azizi returned to his permanent position at the University Sains Islam in Malaysia, and Andrew has continued as a post-doc here with us working in the DreamCloud project.


Monday, 9 February 2015

Edible paper

Today my PhD students and postdocs surprised me at the RTS group meeting with a birthday cake in the form of a research paper, IEEE style and everything.

Here's a photo of the cake:


And here is a link to the PDF version of the paper, which I heard went through several rounds of review by the students and postdocs.

Below, some pictures of me cutting the cake and distributing to the Real-Time Systems Group folks.






Thank you very much, everyone! I really appreciated the surprise and all the creativity that went into the paper writing (and baking!)


Random news

Some news that I should have announced earlier here:


  • The book on Embedded Systems Design that I have edited jointly with Alessandra Bagnato, Imran Quadri and Matteo Rossi has been published by IGI Global. It provides insights from the computer science community on integrated systems research projects taking place in the European region. It covers a diverse range of design principles covered by these projects, from specification at high abstraction levels using standards such as UML and related profiles to intermediate design phases.